1. Field of the Invention
The present invention relates to the field of CMOS Integrated Circuits, specifically circuits for switching high voltages on chip in non-volatile memory integrated circuits.
2. Prior Art
Integrated circuits which operate with two or more power supplies invariably require signals to interface between sections of the circuit supplied by different power supply voltages. Multiple power supply voltages may be supplied from external power sources, or, in the case of several classes of integrated circuits such as non-volatile memories, watch circuits and display drivers, may be generated internally or on-chip from a single power source. However, the voltage range over which a signal swings is often incompatible with other sections of the circuit. For example, logic signals with a smaller voltage swing than the circuits to be controlled, may violate the maximum low levels or minimum high levels required by said circuits. In the case of CMOS integrated circuits, violation of the logic signals may result in malfunction of the circuit due to unrecognizable logic signal levels, and also in simultaneous conduction of PMOS and NMOS devices, thereby increasing the operating current of the circuit. Signals generated from a higher supply than the circuit to be controlled may also cause malfunction. As an example, if a high voltage signal is routed in diffusion into a low voltage region of an integrated circuit, the integrated circuit may be driven into SCR latchup. A level shifter solves the latchup problem by converting or shifting its output signal to a voltage range different than the voltage range of its input signal.
FIG. 1 illustrates a typical prior art high voltage level shifter. Referring to FIG. 1, a low voltage logic signal is applied to input node IN, which is also applied to the gates of P-channel and N-channel devices N1, N3, and P3. This may be, by way of example, a 0 to 2.5 volt logic signal. The inverse of the input signal, INB, which is created by the inverter pair N3 and P3, is applied to the gate of device N2. Pull-up P-channel devices P1 and P2 have their substrates and sources coupled to high voltage supply VHV. Signals IN, INB and the sources of devices N1 and N2 are referenced to the same node, VSS. One of the N-channel devices, N1 or N2, is in the conductive state while the other is in the non-conductive state, depending on the polarity of input signal IN. The conducting device pulls its drain voltage to VSS, and since the drain is connected to the gate of the opposite P-channel device P1 or P2, the P-channel device enters the non-conductive state. Consequently, due to the cross coupled configuration, one side of the level shifter is pulled low, turning on the opposite pull-up device to pull the other side high as referenced to VHV.
During the transition period, when the level shifter is changing from one stable state to the other, a charging current and a simultaneous conduction current passes through the P-channel devices P1 and P2 and N-channel devices N1 and N2. However, with correct design of device dimensions, the level shifter nodes continue to change voltage until output nodes HVOUT and HVOUTB are at opposite potentials, one at high voltage supply level VHV and the other at VSS. In the stable state, there is no current through either of the two current paths, P1/N1 or P2/N2, because one pair has VSS on the gate of the N-channel device, holding it off, while the other pair has high supply voltage VHV on the gate of the P-channel device, holding it off also.
The P-channel devices P1 and P2 of the level shifter of FIG. 1 are potentially subjected to gated diode breakdown, BVDP, and P+ drain to n-well junction breakdown, BVJP, at their drains. The N-channel devices N1 and N2 of FIG. 1 are also potentially subjected to gated diode breakdown, BVDN, and N+ drain to P-substrate junction breakdown, BVJN. To avoid such breakdown, all the breakdown voltages are required to be larger than high supply voltage VHV, i.e., 21 volts in the example given. To accomplish this, special high voltage process steps, such as using double diffusion junctions on the source and the drain of the high voltage P-channel devices P1 and P2 and high voltage N-channel devices N1 and N2, are used to minimize the electric field across the source and drain junctions. Such special high voltage steps are generally undesirable.
A high voltage level shifter utilizing only low voltage PMOS and low voltage NMOS devices. The high voltage level shifter is used to distribute the high voltage almost equally among the PMOS devices and almost equally among the NMOS devices to meet the device electrical specification of low voltage MOS devices for various breakdown mechanisms. A layout technique is also used to achieve a much higher junction breakdown of N+ drain to P-substrate and a better gated diode breakdown of NMOS devices.